Jtag what does it do

Those modules let software developers debug the software of an embedded system directly at the machine instruction level when needed, or more typically in terms of high level language source code. System software debug support is for many software developers the main reason to be interested in JTAG. Frequently individual silicon vendors however only implement parts of these extensions. There are many other such silicon vendor-specific extensions that may not be documented except under NDA.

All of this is controlled from a serial data path called the scan path or scan chain. Figure 3. Basic principles of an interconnect test. Because each pin can be individually controlled, boundary-scan eliminates a large number of test vectors that would normally needed to properly initialize sequential logic. Using JTAG, tens or hundreds of test vectors may do the job that had previously required thousands. Boundary-scan enables shorter test times, higher test coverage, increased diagnostic capability, and lower capital equipment cost.

The principles of interconnect test using boundary-scan components are illustrated in Figure 3. Two boundary-scan compliant devices are connected with four nets. The first device includes four outputs that are driving the four inputs of the other with predefined values. In this case, we assume that the circuit includes two faults: a short fault between Net2 and Net3, and an open fault on Net4.

We will also assume that a short between two nets behaves as a wired-AND and an open fault behaves as a stuck-at-1 condition. To detect and isolate defects, the tester shifts the patterns shown in Figure 3 into the first boundary-scan register and applies these patterns to the inputs of the second device. The standard accounts for the addition of device-specific instructions and registers that can be used to interact with additional IC capabilities.

More recently, embedded IC instrumentation—from instruments that measure voltage and current to devices that can execute high-speed test on the chip—has used the JTAG TAP as the access mechanism, providing new visibility into the IC and further expanding the scope of JTAG testing.

The input values captured in the boundary-scan register of the second device are shifted out and compared to the expected values. In order to add this open circuit coverage it is necessary to communicate with the peripheral device from boundary scan on the enabled device. If communication can be verified, there cannot be an open circuit fault.

This type of testing can be very simple, for example lighting an LED and asking an operator to verify it has activated, or more complex, for example writing data into the memory array of a RAM and reading it back. The library files contain models for all types of non-JTAG devices from simple resistors and buffers to complex memory devices such as DDR3.

Because boundary scan disconnects the control of the pins on JTAG devices from their functionality the same model can be used irrespective of the JTAG device controlling a peripheral. Most boards already contain JTAG headers for programming or debug so there are no extra design requirements. In order to run any boundary scan based testing it is necessary to have some information about the implementation of JTAG on the enabled devices on a board. Not at all. One of the key benefits to boundary scan testing is that the only test hardware required is a JTAG controller.

Using boundary scan during board bring-up can remove uncertainties — hardware engineers can test prototype boards for manufacturing defects before system testing, and even before firmware is complete. This has since become a standard emulation debug method used by silicon vendors. JTAG can also provide system level debug capability. Having extra pins on a device provides additional system integration capabilities for benchmarking, profiling, and system level breakpoints.

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Enter your email below, and we'll send you another email. Thank you for verifiying your email address. We didn't recognize that password reset code. We've sent you an email with instructions to create a new password. Skip to content Search for:. Test process The standard test process for verifying a device or circuit board using boundary-scan technology is as follows: The tester applies test or diagnostic data on the input pins of the device. The boundary-scan cells capture the data in the boundary scan registers monitoring the input pins.

Data is scanned out of the device via the TDO pin, for verification.